The present invention relates generally to structured application-specific integrated circuits (“ASICs”), and more particularly to methods and apparatus for programmably powering down such structured ASICs.
So-called structured ASICs are sometimes used as alternatives to programmable logic devices (“PLDs”), such as field-programmable gate arrays (“FPGAs”). An FPGA has a generic structure that may include many identical blocks of logic circuitry, many registers, and a number of other types of circuit blocks, such as I/O blocks, RAM blocks, DSP blocks, PLL/DLL blocks, etc. These various circuitries are programmable to perform any of a variety of tasks. An FPGA also has a generic interconnection structure. This structure is programmable to interconnect the other circuitries on the device in any of many different ways. The logic blocks of such an FPGA may be referred to as logic elements, logic modules, adaptive logic elements, or adaptive logic modules (“LEs”, “LMs”, “ALEs”, or “ALMs”).
A known type of structured ASIC equivalent to an FPGA has a generic structure that includes many identical instances of a relatively simple circuit block (a so-called hybrid logic element or “HLE”). The structured ASIC may also generically include other blocks that are comparable to the special-purpose blocks on a related FPGA (e.g., I/O blocks, RAM blocks, PLL/DLL blocks, etc.). These generic attributes of the structured ASIC are embodied (at least to some extent) in several of the masks used to make the ASIC. These masks can therefore be the same or substantially the same for all ASICs of this general kind, and they give the ASIC its “structure.” Other masks (but only some of the total mask set) are customized to give the structured ASIC particular functionality that is equivalent to the functionality of a related, programmed FPGA. For example, these customized masks may configure an HLE or a small group or cluster of HLEs (a complex HLE or “CHLE”) to perform functions equivalent to those performed by an ALE in the related programmed FPGA. Similarly, the customized masks may configure a CHLE to perform functions equivalent to a register in the related programmed FPGA. The customized masks may also provide interconnections between HLEs, CHLEs, and/or other circuit blocks on the ASIC. These interconnections will typically include interconnections equivalent to those provided by the programmable interconnection resources of the related programmed FPGA.
Therefore, a structured ASIC typically has a number of fixed layers including fixed semiconductor layers and fixed metallization layers, with provisions for one or more programmable layer (metal or via, as described below in more detail) to be added to implement the design of the related programmed FPGA. Among the structures in the fixed layers are I/O ports, which may or may not be used in a particular FPGA design.
Using a structured ASIC of this kind and in this way has a number of advantages. For example, only some of the ASIC masks need to be customized. This tends to reduce ASIC cost and to speed up the ASIC design/production cycle. It also reduces the risk of a design flaw in the ASIC, and it facilitates producing an ASIC that is a close operational equivalent to the related programmed FPGA (e.g., pin-for-pin identity, timing identity or near identity, etc.). Another advantage of this approach is that it tends to allow the ASIC to include less circuitry (including less circuitry for normal operations) than the related FPGA. This is so because only as many ASIC HLEs as necessary are devoted to performing the functions of each FPGA ALE, and in almost all FPGAs many ALEs are less than fully utilized.
Efficient and reliable conversion from FPGA designs to structured ASIC designs (and vice versa) is important to provision of FPGAs and ASICs that are equivalent to one another. For example, after a design has been proven in an FPGA, it may be desired to migrate that design to an ASIC in order to lower unit cost. As another example, it may be desired to use an FPGA to prototype a design that is really intended for ASIC implementation. However, in a typical structured ASIC design, some active devices are unusable due to routing or placement constraints. Presently, to reduce the leakage power through the device, filler cells are used to fill in this unusable area and all of the inputs of the unused device are tied to a power source. While this approach may help to reduce the leakage power through the unused device, there is still a small amount of current that will flow through the stable state device as a leakage current. In deep sub-micron technology, the steady state or off state leakage current becomes higher and introduces a significant impact to the overall power system.
Accordingly, it would be desirable to provide methods and apparatus for programmably powering down a structured application-specific integrated circuit by totally disconnecting the power source from the unused device to reduce the leakage current.